Result-from-carry adder-subtracters



- June 1959 J. v. B LANKENB-AKER 2,892,587 I RESULT-FROM-CARRY ADDER-SUBTRACTERS,

4 Sheets-Sheet 1 Filed Sept. 5, 1953 IN VEN TOR.

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292 mm, b. I //.r 177414417X I. II I I II I I I I 05-441 2 aim r J. V. BLANKENBAKER 'RESULT-FROIvFCARRY ADDER-SUBTRAC'IQERS Filed Sept. 3, 1953 June 30, 1959 4 Sheets-Sheet 2 June 30, 1959 J. v. BLANKENBAKER 2,892,537

.RESULT-FROM-CARRY ADDER-SUBTRACTERS Filed Sept. 3, 1953 4 Sheets-Sheet s FIG: 7a.

INVENTOR. JOHN V. BLANKENBAKER ,4rroeA ix June 30, 1959 J. v. BILAINKENBAKER v RESULT-FROM-CARRY ADDER -SUBTRACTERS 4 Sheets-Sheet 4 4 Filed Sept. 3, 1953 FIG; 8.

Fra. 55.

Jay/v kfiuwnwanA iz,

INVENTOR.

Arrazmzx United States Patent This invention relates to result-from-carry adder-subtracter's and, more particularly, to binary or binary-coded I decimal adder-subtracters wherein the result is' formed as a function of the binary carry series, no separate sum or difierence producing network being required;

Many adders, subtracters and adder-subtracters' are presently known wherein the binary carry series and re-' sult, either sum or difference, are formed through separate networks, except for the inclusion of a delayed carry signal in the sum or difierence producing network. Such circuits, for example, are describedand claimed in copending U.S; patent application Serial No. 189,318, for Arithmetic Units for Digital Computers, by E. C. Nelson, filed October 10, 1950, now abandoned.

The present invention contemplates a novel addersubtracter circuit where the result digits which are formed are produced as a function of the carry signal produced at the same time, rather than the delayed carry signal usually utilized. By utilizing the novel binary result from-carry adder-subtracter of the present invention in combination with binary-coded decimal correction networks, it is possible to form a result-from-carry binarycoded decimal adder-subtracter wherein the desired binary-coded decimal result is produced directly as a function of: the binary carry series; the signals-produced by a comparison flip-flop indicating when the binary carry digits are equal to the binary sumof difference; and the signals produced by the correction flipfiops required in the correction network. Thus, it is not necessary to separately produce a signal series corresponding to the true binary sum or difierence.

With the adder-subtracter of the present invention, therefore, it is possible to considerably simplify binarycoded decimal arithmetic units wherein the true binary result is separately produced and then corrected toprovide the desired binary-coded decimal result; the general design of such arithmetic units being described in two' copending US. patent applications. In the first copending application Serial No. 278,408, for Arithmetic Units for Decimal-Coded Binary Computers, by' D. L. Curtis, filed March 25, 1952; both serial and parallel arithmetic units are considered, each of the several em bodiments disclosed including a correction control network which produces a control signal when the true binary result is not in the desired binary-coded decimal form. A correction transfer circuit, responsive to the control signal, is utilized to correct the true binary result to the desired binary-coded decimal form when the necessity therefor is indicated by the control signal.

An improved circuit for correcting the true binary result to the desired binary-coded decimal result is de' scribed in a second copending U.S. a plication Serial No'. 322,665, for Serial Arithmetic Units for Binary- 1 the special correction circuits associated 2 Coded Decimal Computers, by E. C. Nelson, filed No vember 26, 1952, now Patent No. 2,823,855. The feature of the circuit disclosed in the second copending application is that the true binary result is shifted and corrected in a single operation,- making it possible to'reduce the amount of storage capacity required to record the numbers as Well as the amount of time required" in adding input numbers. The second copending applicaf tion to Nelson contains a considerable amount of description concerning the logical design of shifting and correcting binary-coded decimal arithmetic units and therefore is incorporated into the present specification by way of frequent reference, being referred to simply as the above-mentionedcopending application to Nelson.

In the circuit of the copending application to Nelson the true binary result signal and the binary carry signal produced by the separate networks are utilized throughout the binary-coded decimal correction circuits so that, in practical applications, it is necessary to introduce a buffer flip-flop between the binary result producing network and" the correction network. During the correction period, then, the buffer fiip-flop stores' the fourth binary digit, referred to as RH, and the carry flip-flop the fourth binary carry Cb, representing in effect the fifth result digit. As will be more fully understood after the present invention is considered in detail, theintro'duction of the buffer flip-flop changes the timing of the correc' tion operation so' that during the time a binary-coded decimal correction is made upon one group of four binary signals, the first binary result signal or the next group offour digits is being produced by the binary result producing network. As a result, decimal carries produced during the corrections mustibe half-added to the; true binary result or corrected decimal result later during the adder-subtracter operation. A special correction of this type necessitates additional gating circuits which are not required in binary-coded decimal adder-subtracters utilizing the present invention; since, according to the present invention, the first binary result digit of the next group has not yet been formulated during the binarycoded decimal correction of the previous group. Thus, it is possible to enter the binary-coded decimal carry's'ige ual into the binary carry flip-flop, efiectively adding it to the next group of signals.

As will be more fully understood from the following descriptiom the comparison flip-flop required in ernbodi merits of the present invention is not an additional flipsflop since it operates as well as a bufler flip-flop'isol'ating the correction circuits from the binary carry producing circuits; Thus, the present invention makes possible an economy in gating circuits without necessitating any additional" flip-flops. v f- In general, the binary-coded decimal correction-circuits utilized in combination with the present invention are based upon the basic principles explained in; detail in; the above-mentionedcopending application to Nelson. These principles, therefore, are only briefly considered herein, reference for further details being made to the copending application. In a few instances, however, itis convenient to introduce" new analysis techniques which facilitate the development of logical equations defining was the res: ent invention; r

It will be established, moreover, that the result-fro carry technique taught bythe present invention 'rnak possible a simpler binary-coded decimal correction pr cedure wherein the decimal carry and fourth laiiiarydigit of the decimal result (Rd are produced during one time interval, and the second and third binary digits of the decimal result (Rd and Rd are then formed during a second time interval, the decimal carry signal (Cd) and fourth binary digit signal (R11 previously produced being utilized to simplify the correction. The time-shar ing correction thus made possible allows a considerable reduction in gating circuit levels as well as a reduction in thenumber of gating elements required.

According to the present invention a true binary resultfrom-carry circuit is provided which includes a flip-flop C for storing the binary carry series and a flip-flop Q for storing a series of comparison signals indicating the correlation between the carry signal and the corresponding binary result signal Rb. Since signal Rb may be derived from the carry and comparison flip-flop signals with a very simple gating circuit, it is possible to utilize signal Rb throughout the binary-coded decimal correction circuits without the addition of an additional buffer flipflop as is ordinarily required where signal Rb is separately produced through a separate network. While generating signal Rb as a function of signals C and Q allows an economy of gating circuit elements, a greater number of gating levels are required than are used in correction circuits operating directly from signals C and Q.

For some applications, therefore, it is desirable to perform the binary-coded decimal corrections directly as a function of complementary carry signals C and C and complementary comparison signals Q and Q; thus reducing the number of gating levels required and eliminating entirely the necessity for separately producing a signal series Rb. Finally, the correction process may be further simplified, in terms of gating elements required, by first producing the desired binary-coded decimal carry signal Cd and entering signal Cd into the carry flip-flop C; and, at the same time, entering a comparison signal Q into flip-flop Q corresponding to a corrected decimal result digit. Signals C, C, Q and Q are then utilized in a second correction process during which the decimal digits Rd and Ra are produced.

Accordingly it is an object of the present invention to provide a novel result-from-carry binary adder-subtracter.

Another object is to provide a binary result-from-carry circuit which may be utilized with binary-coded decimal correction circuits, obviating the necessity of a separate true binary result generating network.

It is also an object of the present invention to provide a simply mechanized circuit for adding or subtracting a pair of serially-applied decimal numbers, of which the decimal digits are represented by binary digits according to the 1-2-4-8 code. An additional object is to provide a result-from-carry binary-coded decimal adder-subtracter wherein a resultto-carry comparison flip-flop is utilized as a bufier stage making it possible to correct for binary coded decimal carries without additional half-adder correction circuits.

A further object is to provide an improved serial binary coded decimal adder-subtracter wherein the desired binary-coded decimal result is produced directly as a function of the true binary carry and a comparison signal, without a separately produced true binary sum or difference signal.

Still another object is to provide a serial binary resultfrom-carry adder-subtracter including a carry flip-flop C and a comparison flip-flop Q, the true binary result being representable as a function of signals C and Q.

Yet another object is to provide a serial binary-coded decimal adder-subtracter including flip-flops C and Q storing the true binary carries and carry-to-binary result comparison signals, respectively; the binary-coded decimal correction signals being derived from signals C, C, Q and Q, no signal Rb, representing the true binary result, being required.

Yet a further object is to provide a result-from-carry binary-coded decimal adder-subtracter wherein corrections are performed on a time-sharing basis making it possible to reduce the number of gating elements required.

The novel features which are beileved to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which several embodiments of the invention are illustrated by way of examples. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

Fig. 1 is a schematic diagram of a serial binary resultfrom-carry adder-subtracter according to the present invention;

Fig. 2 is a schematic diagram of a serial binary-coded decimal result-from-carry adder-subtracter wherein a signal Rb is produced as a function of the true binary carry signal C and the comparison signal Q;

Fig. 3 is a schematic diagram of a serial binary-coded decimal result-from-carry adder-subtracter wherein the desired coded decimal result digits Rd are derived directly ifIOHl the signals C and Q, no network for signal Rb being required;

Fig. 4 is a schematic diagram of a binary-coded decimal adder-subtracter wherein the true binary to decimal correction is performed on a time-sharing basis;

Fig. 5 is a schematic diagram of a flip-flop circuit, and Fig. 5a illustrates a symbolic representation of the flipflop;

Fig. 6 is a schematic diagram of a logical and gating circuit, and Fig. 6a shows a symbolic representation of the an circuit;

Fig. 7 is a schematic diagram of a logical or circuit and Fig. 7a is a symbolic representation of the or" circuit;

Fig. 8 is a schematic diagram of a complementary signal generating network suitable for use in mechanizing the invention;

Fig. 8a shows a symbolic representation of the complement generator; and

Fig. 8b shows wave shapes illustrating the operation of the complement generator of Fig. 8.

Reference is now made to Fig. 1 wherein there is shown a serial binary result-from-carry adder-subtracter according to the present invention. As shown in Fig. l, the adder-subtracter includes a carry flip-flop C for producing complementary carry signals C and C corresponding to carries resulting from the addition or substraction of input signals A and B; and a comparison flip-flop Q for producing signals Q and Q indicating when the carry digit produced is equal to the corresponding sum or difference digit Rb.

Flip-flops C and Q are controlled through separate logical gating circuits 10C and 10D, respectively; and the binary result signal Rb is produced by gating circuit 10R. The logical gating circuits are mechanized according to logical Boolean equations which define the signals which the gates produce. Before the invention may be fully understood, therefore, it is necessary to consider the derivation of these logical equations. In the equations and tables which follow the subscript j is utilized to indicate binary digit position of the input information. Thus, symbols A,- and B represent the j binary digits of the input numbers A and B. The carry C,- represents the carry digit resulting from the addition or subtraction of the f column of the input information. Similarly, carry C,- represents the carry digit derived from the previous column of the input information, which is to be included in the addition or subtraction of the i column of the input information.

- An algebraic representation of variable Q 8,, and Cf be di-ivd 6651 trhth'TabIe 1'; shown 7 wherein all of the possible binary numbe'r' situations are included for the variable A;; B, and C,

TableI plus B) h 7 V 5 4 Bi Q e?! HOt-(OHQHC HOQHOHI-IO "t ny-06cc mucousc ravageoms;

, woocgcov- 'Asindicatediii"Table"I,:tlie sum digits, is equal .to the new carry' C,-+ only when A,; Bf, and-Cp are all equal to Q or-all equal'to 1. ..Defini ng0,+, then,-as a variable or signal which is equal to 1 when 8; equals (3 Qf may be represented algebraically as:

- Q? =Z}.F,-;'C A,-;B,- 0, 1, p 61 H- t-I' i1) --(i+ i+ i1i where the" dot is the log'icaPand" the'bar re'presents'a: complement, and the plus is the logical.nonexclusive or. The function for Q,- then is interpreted as follows: Q is 1 when A}; B,-, and'C,- +are equal to 1 oiwhen eeni lementgry signals 3;, 13, and @g gare seen to 1"(A}, 1a,, and c, being equ'allto 0 1 With t e a i Qii an Q1 t ..,de u d he v ables'S; may menus Written in terms ofC,-+ and Q as renews:

As is more fully explained in the above-mentioned copending application to E: 'C.- Nelson, Serial No. 189,318, the complementary carry signals Cf and (3 may be defined as renews: I

In a similar manner the comparison, difference, and carry signals for the subtraction of-B fro'rnfA (A-B) may be derived from ,Table II below. These functions are indicated below Table II as functions Q3, D and C respectively;

Table II (A minus B) Rule 1;, B; 0;, 0; I Rb,=1),-

o 0 0 0 1 0 0 0' 1 1 1; 1 0 1 0 1' 1 1 0 1 1 1 a 0' 0 1 0 r 0 0 0- l 1 1 0 1 0 1 0 1 1 0 0 1- 0 1 1 a 1 1 1 1 1 With the introduction of the sign indicating signals S and S complete add-subtract,- result-from-carry functions may be provided; signals and being defined so that they are equal to 1 and 0, respectively, during subtraction, and 0 and 1, respectively, during addition. I

Table I I-A indicates-f new the various signals are com: hined to' obtain tlie desired result? Certain quantities shown in Table Il-A' are enclosed within a block. These quantities include the input quan tities A and B and a carry C from the previous binary position: These quantities are used as independent vari ables in determining the comparison quantity Q, the carry C from the binary position undergoing computation to the next binary position and the output quantity Rb representing the arithmeticcombinati'on of A and B on a binary basis. The quantities C Q5, and R5 are considered as dependent variables and are indicated as such by asterisks in Table II-A, Similar combinations of signals occur in" the successive timeintervals. The completeequations'then are: I Q1 iii l+ ii Ci-1+ ii-1'+ ii'-1) i='"Q; ,-*+Q?- V I =B .C +S.(Ajj1 +S.(A,'.Ci l 17+ wherethe symbol denotes abinary digit, Variable 're lated to the 1 5 1 column of input information, and???- pre'sse'df in terms of both additionand' subtraction opera tions. r

' Before considering the mechanization of logical g'at,- ing circuit" IOC and lOQ it is necessary to'consider'tlii generalforr'rifof equations defining the inputtuiictioris'for' flip-flops. The discussion here isibrief since the general theory of flip-flop control function'sis discussed in" con: siderable detail in the above-mentioned application by E. C. Nelson as well as in'the following copending applications: Serial No. 327,567, for Binary-Coded Flip Flop Co'untersfbylE; C. Nelson, new Patent No; 2,816,223, and Serial Noi 327,131, for Binary-Coded Flip-Flop Counters, by R. R. Johnson. 7 I Flip-flops C and Q shown in Fig. 1 are assumed to be conventional flip-flops having 1 and 0 input" circuits such that pulses applied separately to the 1 and 0 input circuit of a flip-flop set the flip-flop to stable states representing binary 1 and 0, respectively; and the simultaneous application of pulses to' both 1 and 0 input circuit of aflip-flop triggers theflip flop' or causes'it to change its stable state from 1 to 0 or from 0 to 1. It should be understood-, however, that other types of flip-flops may be utilized provided that it is controlled through a properly mechanized logical gating circuit. vFor example, it will be shown that an overriding flip-flop may be utilized where the Boolean equation defining'the controlling logical gating circuit indicates the conditions where the flip-flop is to be set to 1, regardless of its previous state. In utilizing an overriding flip-flop pulses are continuously applied to the 0 input circuit of the flipflop so that it is set to 0 unless the logical gating circuit conditions are satisfied, in which case a pulseis applied to the 1 input circuit of the flip-flop overriding 'tlie pulse applied to the input circuit and setting the flipflop to 1.

Three general types of flip-flop input functions may be utilized to control the sequence of stable states of an associated flip-flop. According to one type of equation, the sequence of stable states of the flip-flop are directly defined so that the value of the equation (1 or 0) at a particular time indicates the next flip-flop setting. This type of function may be referred to as a setting function. When a setting function is utilized the flip-flop must be an overriding flip-flop of the type just described or a complementer circuit must be introduced to translate the gate output signal into complementary signals. As shown in Fig. 1, gating circuit lOQ is mechanzed according to a setting function and a complementer circuit CO is utilized to translate the output signal of gate IOQ into complementary signals which are applied to the l and 0 input circuit of flip-flop Q. A circuit suitable for providing the desired complementary signals is described in copending U.S. application Serial No. 308,- 045, for Complementary Signal Generating Networks, by D. L. Curtis, filed September 5, 1952, now Patent No. 2,812,451.

According to a second type of defining equation, the conditions for changing the flip-flop stable state or triggering the flipflop are established. When this type of mechanization is utilized, a conventional flip-flop is employed and the gating circuit signal is applied to both 1 and 0 input circuits of the flip-flop.

In many situations, the changing type of equation may be separated into two partial-changing functions which separately define the conditions for changing the associated flip-flop stable state from 0 to 1, and from 1 to 0. The partial-changing functions are particularly useful where the equations include the output signals of the flip-flop to be controlled. In this case the partial-changing functions may be simplified according to rules which are briefly considered below and fully described in the above-mentioned copending applications by E. C. Nelson and R. R. Johnson.

The setting, changing, and simplified partial changing functions for controlling a flip-flop Fj (j representing any flip-flop) are designated respectively by the notation: i Fj=; 1Fj=0Fj=; and 1Fj=, and 0Fj=, respectively.

As is more fully explained in the above-mentioned copending applications to E. C. Nelson and R. R. Johnson, any flip-flop function may be written in the form: t Fj=FiG+FLfi, which may be reduced to the simplified partial changing functions:

0Fj=H G and H being any functions of variables other than F and 1W, where F and Ii are the signals produced by flip-flop F1.

The carry function for flip-flop C may be written as: 1 C=C.(B+S.A+S.E)+(C+G).(S'AB-FSJLB) where the functions (S.A.B+S..B) and (B+.A+S.zi) correspond to the functions G and f1 above. Thus, the carry flip-flop input function may also be written as: (C) lC=(.A.B+S.Zf.B).Cp

OC=(S..Z.J+S.A.1).Cp

where signal Cp is introduced to indicate a synchronizing and condition, signal Cp occurring once each binary digit time interval.

The equation defining the input circuit for flip-flop Q is most conveniently written as a setting function in the form:

and output gating circuit 10R is mechanizedaccording to the functions 7 In these functions it will be noted that the actual flipflop signals have been substituted for the variables discussed above; thus, A, B and C correspond to A B and C,- discussed above. U

As is indicated in Fig. 1, each of the and functions in the equations defining gating-circuits 10C, IOQ, and 10R (in corresponding equations shown above) is provided by an an circuit which responds to signals applied to separate input terminals and produces'a 1- representing output signal only when all input signals are l-representing signals. Thus, an circuit IOQ-l, in gating circuit 10Q responds to signals A, B, and C applied to separate input signals and produces a l-representing output signal only when all of signals A, B, and C are l-representing signals. Similarly, and circuits 10Q-2, 10Q3, and 10Q-4 respond to separately applied input signals to produce the l-representing output signal defined by the corresponding and function.

Each of the or functions in the above equations is provided by an or circuit which responds to separately applied input signals and produces a l-representing output signal when any one or more of the input signals is a l-representing signal. Thus, or circuit 10Q-5 responds to signals representing A.B.C, 5.3.6, S.B.O", and S.B.C applied to separate input terminals and produces a 1- representing output signal when one or more of these and conditions is fulfilled.

The manner in which the other logical circuits are mechanized should be apparent from the examples considered. The operation of the binary result-from-carry adder-subtracter is illustrated in Table III below which illustrates a binary time sequence function of the various flip-flop signals during a typical operation.

Tablelll As indicated in Table III the final sum or difierence signal series are produced after a delay of one binary digit time interval, so that the least significant digits of Sb and Db are produced during the second time interval of Table III. The operation of the logical circuits maybe noted in Table III. The carry flip-flop C is set'to 1 after the first occurrence of the condition A.B=1 (see 0 for addition and remains 1 until the first condition 113:1 when it is set to 0; similarly, in subtraction, flipflop C is set to l for 1.13:1 and to 0 for 113:1.

During addition or subtraction flip-flop Q is set to 1 one binary digit time interval after all of signals A, B, and C are 0 or 1. In subtraction flip-flop Q is also set to 1 after either B1? or 152C is 1. Both the sum and difference functions are defined by the function:

occurring during the same time interval.

When the binary result-fromcarry adder-subtracter is a binary-coded Jana systeniit: i; sary. to make correction for the situation where-a i. dec mal Cd'is requires and must be entered into ni fiopi (C, It is" also n cessar to modify the funcnen fo ffiip flop Q since the. decimal carry creates certain situations where signal C is not equal to R unless the decimal carry is specified as 1 or 0.

A complete carry function with the decimal carry Cd included may be determined from Table IV below, wherein the signal Cd is introduced as a quantity having the value of 1 1 0. lt will be noted that Cd is always 1 when the binary carry C is 1.

Table IV (A plus B) at B:- wt-oi 4 .1 1, Q'-

1 0 0 a ca 0 ca- 1 6a 2 o o 1) 1 o 0 s o 1 0 oa e11 3a 0 1 o 1 (1 1 1 0 0 a 1 o (0 ca oa 6a 0 7 1 1 (0) or 1 ca 0a a 1 1 1 1 1 1 1 Whereas Table I illustrates the relationship which ap plies for ordinary binary addition, Table IV is intended to particularly illustrate the results of the additioiiof the first binary digits of a pair of decimal digits or the numbers A and B. The binary digits to be added" are A B and Cd, where Ca represents the decimal carry resulting from the addition of the previous pair of decimal digits of the input numbers. In this particular case since A, and B, represent the first or least significant binary digits of a new pair of decimal digits, C,' represents 40 the true binary carry resulting from the addition or the last pair of binary digits of the previous pair of decimal digits. Whenever C,- is 1, Cd is also 1; when C,-;f+ is 0 the value of Cd is indeterminate and hence is indicated simply as Cd. Thus according to rule 5, for example; the new carry signal C,+ (resulting from the addition of the first binary digits of the new pair of decimal digits) will have the same value as Cd, whereas the true sum have the opposite value. It may be noted that Table I represents a special case for therelationships represented hy'lablelwnamely, the case where Cd'isOI I, v 'Asindicated in "Table IV, a complete addition carry function may be expressed as follows:' I

- 1 i i-1+ ii i+ i)' 'C B.-+ Cd A',-+ 1+Q; I.( A,-+H.-

The carry flip-flopfunction for addition, including the decimal carry then becomes:

1C=[A.B+Cd.(-A+B)].Cp

0C=l.E.Cp Y a'ii'd'; since no carry correction is required' for subtraction, thecdmpl'ete add-subtract flip-flop function becomes: 1c'={s. A.B+cd. A+B +s..B};cp.

0'c'= s.t.1+s.A.B .c In a similar manner the function for flip-flop Qmay seesaw suitable for use with the resmt-nem-enr addef subtr'sij r of the present invention is illustrated in Fig. 2. general correction scheme is based upon principles fully explained in the above-mentioned copending application by E. C. Nelson and the notation utilized herein is consistent with that utilized in this application. As in the copending application, two flip-flops F1 and F2 are included in the correction network; these flip-flops being controlled through logical gating circuits 20F1 and 20F2, respectively. H i

As is more fully explained in the copending application, no correction is required in the first binary digit of the true binary result where excess-even binary codes are utilized and consequently during the correction period, indicated by the timing signal T having a level representing binary 1, it isonly necessary to haye binary information concerning the second, third and'fou'rth binary digits of the true binary result and the fourth carry digit; these 1 digits being represented respectively by the variables Rb,

Rb Rb and Cb As derived in the copending application, the correction indicating signals E and E for the excess-0 binary-coded decimal code are defined as follows:

' n=cb m +Rba a 255C71 R'I3 +1Z' .R'5 Signals E and E define the conditions where the true binary sum is a number which is greater than 9. If the binary carry signal Cb is ,1 the true binary sum is l6,

. 17, 18, or 19; and if the fourth binary result digit is 1 and either the third or second digitisl 1, the.true bina y sum is any of the numbers 10 through 15. As is furtherf 'ing the variable Rb by its equivalent result-from-carry digit. This provides the functions:

' Of particular interest in these function is that the varibe modified as indicated in Table IV to provide the functions:

' z Q=[dd.rl.B'.6+A.B.(Cd+C) .C where the' signal Cd is produced through the binary coded decimal correction network now to be described. H 1, 7 One type of binary coded decimal correction network 1 ference producing network, by the fuiilitionzbQC-f-Q. I

'able R'b is effectively replaced by the variable Q representing the fourth comparison digit. Thus,;. it should? be pp re a fl pp Q w l u ctio nthisr sneet as a buffer flip-flop since it produces a flip-flop signal which substitutes for a matrix signal previously produced by the binaryre'sult producing network. 7

The complete add-subtract correction functions for the excess-0 binary-coded decimal code derived'in the'cop ing application may now be modified with the introdu oni of the redefined" signals E and 1 1' and the replacement of signal Rb with Q6. The functions derived in the copending application appear as follows:

E T.c+T.Rb-.F +r.Rb.F

Equal-moral 1F1= E.F2+s;E.F +s.F .c 0F1=' (.F +E.F +S.E.F .Cp 1F2 (ERb-l-. E. b .F ).Cp 0F2=(EEa-SiERb-l-Sflb+S.E.F ).Cp The" signal Rd in these functions is produced output gating circuit 20R and corresponds to the desired binarycoded decimal result series. 3v V p 3 This set of functions is then modifiedby replacing the signal Rb, previously produced in a separate sum or The new set of funds then appear as follows, the equatiaii numbers shown corresponding to the gating circuits shown in Fig. 2.

p 7 Table V-B indicates the various combinations of signals,-

Cd=E= T.C'+ T.'Q.F Thi 10 Table ETJ=F=T+E +ZIF F (20R) 'Rd=-E.F +T We Q a (20m 1F1= Tr.m+'S.E.'F- +s.m .c 3% :3 g g g g g 0 0F1=(.'F=+EF +S.E.F ).Cp a 4:5 1 o o 1 0 0 0 i tt'ittlttlt (F2) 6 10111 00 1 o 1 1 o 0 ----1 20 tli'littillltl E=[:(Q +Q-E')+ -(QfZ-Q- 'X I P 9 16:17 0 1 0 0 o 1 0 l OF2=[E.(Q.C+Q C)+,S E 10 18,19 0 1 0 0 1 1 1 0 5160+ f +S.E'. F ].Cp Table V-A indicates the time relationship between the various quantities used in the embodiment shown in Figure 2. As may be seen in Table V-B, the decimal sum of Table V-A V Input Flip-flops Fllnflnps Output 'Ilme Slg nal A; B,- CM Qi-X Gd FZI-g Fly-1 Edy-i h 1 A1 B1 C4 Q4 Cd Rb; Rb; Rd,

:1 0 a B, 0: Q; 0 Rd Rd: Rd: t, 0 A; B: C: Q! 0 Rb: Rda Rt! t1 0 A B4 C: Q: (1 RD: R61 Bar -Rb:

h 1 A1 B1 C4 Q4 Cd RD: Rb: Rd:

' t1 0 A: B1 C? Q, 0 Rdi Rd: Rd: t, 0 A: Ba 0: Q: 0 Rb; Rd; Rd is 0 At B4 C1 Q: 0 Bill Rbi Rd1=Rb1 As will be seen in the first vertical column of Table V-A, timing signals t t t and occur on a recurrent basis. These timing signals correspond to the four binary positions required to indicate a decimal digit on a binarycoded decimal basis. Means are provided to obtain the production of a binary "1 signal at correction time interval t and to obtain the production of a binary 0 signal at the other time intervals. Time interval 11; is considered as a correction interval for reasons which will be described in detail subsequently.

Certain quantities are used as independent variables to obtain the production of dependent variables in each time interval. In time intervals t t and t the input quantities A and B are combined with the binary carry C from the previous position to obtain the carry C from that position to the next, the comparison quantity Q and the binary sum Rb. At correction time interval 1 the quantities A and B and the binary carry C; from the previous position are combinedwith the decimal carry Cd to produce the binary carry C the comparison quantity Q and the binary sum Rb These dependent quantities are indicated by asterisks in Table V-A. At the same time, the binary sums for the difierent digits are converted to a binary coded decimal basis represented by the signals Rdg, Rd; and Rd;-

binary-coded decimal input quantities A and B is indicated in the second vertical column. This decimal sum may be represented by a particular pattern of signals for S12 Sb; and Sb The quantities Sb Sb and S11 represent the binary sum of the input quantities A and B in the three positions of greatest significance. The binary value of 8b., is 1 when Q and C both have indications of 0" or indications of l. The binary value of Sb. is 0 when one of the quantities Q and C is 0 and the other of the quantities is 1. This has been set forth in the equations following Table I.

As will be seen, S12 Sb and Sb directly indicate the decimal sum for values between 0 and 93' For such values, the decimal carry Cd is 0. For decimal values between 8 and 15, the values Sb and Sb have a pattern corresponding to the decimal values between 0" and 7 but S12 has a binary value of 1 for decimal values between 8 and 15 whereas Sb has a value of 0" for decimal values between 0 and 7.

The decimal sums between 0 and 19 can be represented by a decimal carry or lack of carry and by a binarycoded decimal representation. For example, no decimal carry is obtained for decimal sums between 0 and 9 and a decimal carry of 1 isobtained for decimal sums between 10 and l9." Since a decimal carry of 1 is were... fo ileq mali iim a e than vs r ecinial' sums can be represented in the binary positions of greatest significance by patterns corresponding to the decimal sums between 0 and 9. This may be seen in Table V-B.

At the beginning of the correction time interval t the binary sums Sb and Sb; are respectively indicated by the F2 and F1 flip-flops. At the end of the correction time interval t the binary values of Rd, and Rd are respectively indicated by the F2 and F1 flip-flops. This may be seen from Tables V-A and V-B. As will be seen from Table V-B, the F2 flip-flop is triggered from a binary pattern of 0 to a binary pattern of 1 in accordance with rules and 10. In rule 5, the carry signal C is 0 and the binary sum for the digit of greatest significance is 1. In this way, the F2 flip-flop can be triggered true in accordance with the logical equation, lF2=E'.(QC+Q.6').

In the above equation E =fid and Sb =Q.(7+Q.C. Similarly, the F2 flip-flop is triggered true in accordance with rule when Cd=E and F1 are true and Sb is false as represented by 1F2=S.E'.(QC+Q.6).

1n the above equation, the term S indicates the addition 9t theainnu qua tit s A and it T s equ q Q J Z are included in Equat-ign ZQFZgset forth abovet Table V-B indicates that the F2 flip-flop is triggered false during the correction. time interval 1 in accordance with rules 3, 4, 7 and 8." Rules 3 and 4 can be represented by an indication of 0" for Cd and for 8b,. This can be Written as OFZ= E .(Q.(7+Q. C). Similarly, rules 7 and 8 can be represented by simultaneous indications of l for Cd and S11 This can be written logically as 0F2=S.E.(Q.C+Q.0"); This logic for DB2 forms a part of Equation F2.

The triggering of the F 1 hip-flop at correction time interval t, can also'be determined from Table V-B for the addition of the -binary=coded decimal input quantities A and B. For example, the F1 flip-flop is triggered true the::ta s as a es ccor an wi r e a Rule-3 can zbe r'epresented by and rule 9. ,can be representedas SLEFZL This logic forms apart of EquatiQnZOFl- I v he l prflop' is t ig r d t am th ru -s e t th false state at correction time interval L; in accordance with rules 2, 6 and 10. Rule 2 can be represented as 1 1.1 2. Rules 6 and 10 can-{be represented as 5.1 2. These terms form apart of Equation 20F1 for OH.

In the correction time intervals. t t and 1 F2 is triggered in a pa tern sqrrespcjndins t9 th binar 811m of A and B for the position undergoing computation and of the carry C from the previous position. This represented as i.

r. t i ii 7. V-C represents the subtraction of B Table V-B represents the addition of B to A.

Quantities Db ','D'b and Dbgin Table V-C represent the As will be seen, these equations also form a part of the :1. ne at ve carry" binary difference between the binary-coded decimal input quantities A and B in thethree binary ipositionsiof greates s gn ficanc h q a e D t a d bstprovid'e a representation of the difference. between A and B in the two positions ,of greatest significance on abinary-coded de imalbasi Q- ,r .1 ff f I Th qi t t el C .Ddi d D si Table V C re me ir e y s r sn s t t e quan t e 9 414 an S43 in Tab e V B' va ue bet e n, *0? an I. ;b tab e :5 n9 r ra i elsirer s snt by ul 7 1. 55 inclusive, apegan gc 'ryof obtained forCdt since 9b iu dtiDdi 'jDds a P i a pa te n q toper t o w eh ep s ts t s e'c a m; element the-ne at e slum r .dsdin H i plement is obtained ad in the nesafiye num erfi a decimal value of +10: 'Forexample;Ddg'and Dtfi a can provide a pattern ofoperation on a complementary basis corresponding to +7'or +8 for a difierence value of -2 or -3.T

The triggering of the F2 and F1 flip-flops at correction time interval t cantheedetennined fromr -Tablewf efi; For example, the F2 flip-flop is triggered true in accordance with rule 10. rule -can be represented as 1F2=E(Q.C+Q.(7). As will be seen, this equation corresponds to logic previously obtained from Table II-B; V i i i Y :The F21flipr-flop is triggered' false at correction time interval 1 inaccordance'with' rules 1, 4, '8, and 9'.' l, 8 and 9 can be represented by the equation In this equatiomnS represents a subtraction operation. Similarly, rule 4 can be represented as S.E.F'l. This logic is included in Equation 20F2.

The F1 flip-flop is triggered true at correction time interval 13 in accordance with rules 4'and 8. These rules can be representediby a common logic of S.F2. Similarly, the F1 flip-flop is triggeredfalse at correction time interval at; in acc-ordance -with rules 1, -5 and 7. Rules 1 and 5 can be represented logically as S.E.F2. Rule 7 can be represented logically as E1 2. All of this logic is in ludedwin E uation zoma The niechaniZation of a serial binary-coded decimal r r l r o a .a de -s btrac e o d n o these fi u tiqns i il u r t d n g- 2, further de a d c92 sideration being deemed unnecessary in iew of the preyiously considered examples and the similarity of this embodimentand that described in the copending appli cation to E. Nelson, p I

'Theoperation ofthe' embodiment of Fig. 2' during a typical addition of binary-coded decimal numbers is illustrated in Table V-D.

The function G. assumes the values of F'- whenever F was (F=1) and the function H' assumes the values of F Table V-D I I I I I I I I I I I l 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 B=1,838.

0 0 0 G 1 0 0 O 1 0 0 0 1 0 0 0 0 0 Cd.

0 0 0 1 0 0 0 1 0 l. 1 1 1 0 0 0 0 0 CD.

0 0 1 1 1 1 1 0 1 0 1 1 O 0 0 1 0 0 BIL I l I I I I I I I I I I The equations defining the circuit of Fig. 2 may be 5 reduced to a form requiring fewer gating levels by substituting equivalent functions for E, 1 Cd and 6d and then simplifying the resulting equations. It is preferred, however, to obtain the expanded function in terms of signals C, C, Q, and Q directly from a truth table indicating the transformation of these signals during the correction time interval when T is equal to 1. Before considering'the truth table derivation, however, it will be helpful to introduce a useful truth table theorem.

As is fully explained in the above-mentioned copending aplication by R. R. Johnson, the transformation of a flip-flop output signal F to a new signal P through input gating circuits defined as:

may be represented by the function:

F'=F'.G+F.E

Analysis of this function indicates that if the flip-flop signal is 0(F=l), F is equal to the previous function G; and that if the flip-flop signal was previously 1 the new signal P is equal to E. This transformation is indicated in Table VI below.

Table VI Rule G H F r 1 o o o o a 2 a 4 o 1 1 0 5 1 0 o 1 s 1 0 1 1 7 1 1 o 1 s 1 1 1 o whenever F was 1. The operation of this principle is well illustrated in Table VI-A below.

In Table VII below, which is derived directly from Table I, the input signal requirements for flip-flop C for producing the binary carry function Cf are illustrated. Symbol lC indicates the signal requirements for the l-input circuit of flip-flop C; and symbol 0C represents the input signal requirements for the O-input circuit of flip-flop C.

Table VI] nine A; B; 07., o; 10 oo 1 o 0 0 0 0 2 0 0 1 o 1 3 0 1 u o 4 0 1 1 1 u 5 1 0 0 o e 1 o 1 1 0 7 1 1 o 1 1 8 1 1 1 1 0 From Table VII it is readily detemiined that the binary carry functions are:

s mmer carry signals 1C from previous :position, theccomparison :signal Qifrom the previousposition and :the binary sum .signals- Rb indicated by the F2 and Flflip flops are used as=independent 'quantiticsto determine the values of other quantities. This may'be'seen'from Table VIILA set'fforth below. 7

Table VIII-A SAs maylbe seenfrom' Table VIH-A, the signal T has abinary'value'of"l at .time't and has a binary value ofat"timest ,t .and t 'Becauseof the .binaryvalue of 'l for Tatitime t ,la correction is made at this time to -convertitheivalues in'the F and F flip-flops from' a binaryfo'rm' to a' binary-coded. decimal form. Thismay be seenffrom' 'the fact that .the value Rb representing the seeon'd digitof the arithmeticcombinationion a.binary basisof the quantities A an'd'iB is converted to the" output value Rd: representingthe'secon'd -digit on a binarycoded decimal basis. The output quantity Rd is actually made available during correction time interval 12;. At the same time,.the value=Rb representing the third digit of the-arithmetical combination-non-a binary basis is converted to a value Kri -representing the. third digit ona binary-coded decimal basis. The value Rd representing the fourth digit on a: binary-coded. decimal basis is also determined at the time t; and is introduced to the F2 fiip flop. In this way the second, .third and fourth digits aredetermindin the correction. time t so as to provide aproper representation. on a binary-coded'decimal basis. The value Rd is made available duringcorrection time interval t but the values Rd;., and R01 are made, available inthe F1. and F2.flip flops'during time interval t As previously described, no correction has to be provided for the first binary digit of a number to convert the number from the binary representation to a binary-coded decimal basis.

"A comparison ofthe techniques used in Figure 3 with theatechnique used. in Figure 2 may be seen from the Tables V-A-arid VIII-A. 'As will be seen, in both tables a correction-is made at time t; in the second, third and fourth digits of a binary-coded decimal number. 'Atthis correction time interval,-the binary carry signal C is used as a common value in both embodiments. However, the

ernbodiment "shown' in'Figure 2 and set forth in Table VA-uses--the.inputjquantities -A and B and the. decimal carry Cd as an additional parameter, whereas. the embodiment shown in Figure 3 and set forth in Table VIII-A uses the comparison value'Q and'the binary re- =sults Rb and 'Rb as additional values. :The quantities used' as independent quantities: in the embodiments set forth in Figur'esZ and-Bare respectively enclosedwithin 1 boxes in Tables V A' and VIII A. The dependent quan tities-determined.from these independent: quantities are indicated by asterisks in Tables -'V'-A and'VIIL-A.

Truth Table VIII, then,- indicates thetransforrnations required in-correcting thcbinary sums to form-the desired binary-.cfidedrdecimalafgii -Asindicated in Table -,VII I, atithe imedhenomection i perform T i qual to 1 n fiip=fl p rand more sign ls ;corre$p ng to Sb2 and S b3,-,;respectively. lhe-;tr-ansformed states of flipflops-"F1 ;and iirthenicorrespond to signals -.Rd and Rd since-the shifting tand simultaneous correction Operation of itheNelson-icireuitsr is .ru ilized.

.rTa ble VIII I Ina-utilizing the sh'iftiirg and correcting functions of Nelson iti will bfi 'notfidmhat when Tds equal-tot) (no correction -being pei formed -the signals in the correcting networkiare=shifited fonward. 't Fhismeans that signal Rb as represented .:by #the result-from-carry functi'on 'QLC-FQZIF -is Shifted iintoYfiip-flop -F2 and that signal F is shiftedtinto flip-fiop Fl. i Utilizing TableVIII; then, theflip flop input functions for addition are found tobe:

'Table indicates'ithepattern in which the F2 and F1 j'flip flopsf are triggered at. correction time L; to, convert fromsithej biparypattern to a binary-coded decimal representation. The second vertical .columnof TableVIII indicates thedecimal sum bffthe; binary-wdeddecimal q a i yifAmiesa d'Atan he in yr de d im q a y '"BeaBzJ Mnd 34- .Sin eac of t bina yd quai t t s'Aafid? B;-.m yl.h v dec al. va1ues.bew e f f0? n .ili9,." the, de .ima .s mrmayr ha a range between"() a'r'rd18." additional carry of 1?f,vmay Occur rom t erithmsfiesqmh nat on ther evious binary-Coded delciniahquantities A and"B;,so.thatitherange of decimal values-mayextend from '0 to 19.

In Tabl vlll only the "secondrthi'rd and v fourth binary digits'of thebinary sum-of Aend-B areshown. 'Th ese binary digits are represented asSb-i, Sb; and Sb The value of Sb, is indicated by a pattern of signals representing the binary carry C from the previous position and the comparison value Q from the previous position. The binary value of 8b.; is 1 when both Q and C are or both Q and C are 1. Similarly, the binary value of Sb; is 0 when only one of the quantities Q and C is true and the other quantity is false.

In each horizontal row in Table VIII, the signals Sb S and Sb, have a pattern corresponding to the decimal value in the second vertical column of the table. For example, a decimal value of either 4 or 5 is represented by a pattern of 010 for Sb Sb; and Sb, respectively. The decimal value is 4 when Sb; is O and is 5 when Sb, is "1. Similarly, a decimal value of either 14 or is represented by a pattern of 111 for Sb Sb and Sb: respectively. A decimal value of 18 or "19 is represented by a pattern of 001 for Sb Sb and Sb; respectively and a binary carry of 1 from the position 8b., to the next position.

The vertical columns designating Rd and Rd indicate the desired binary-coded pattern for the two digits of greatest significancewhen the decimal sums have the diflerent values set forth in the second column of Table VIII. For example, a decimal value of either 8 or 9 is represented by a binary pattern of 1000 or 1001, where the least significant digit is at the right. In either case, the second, third and fourth most significant digits respectively have values of 0, 0 and 1." Similarly, decimal values of 14" and 15" are respectively represented by patterns of 1110 and 1111. where the least significant digit is at the right.

As may be seen from'Tables VIII rmdVlII-A, the binary values Sb and Sb are respectively indicated by the pattern of operation of the F1 and'FZ flip-flops at the end of the i time interval. The F1 and F2 flip-flops indicate the two most significant digits Sd and Sat, on a binary-coded decimal basis at the end of the correction time interval t.;. The required introduction of signals to the F1 and F2 flip-flops during the t time interval is indicated in the last four vertical columns of Table VIII. The triggering signals introduced to the F1 flip-flop are indicated in two vertical columns andthe triggering signals introduced to the F2 flip-flop. are indicated in two vertical columns. For example, the-F2 flip-flop has a first vertical column designated "11 2". and-a second ver tical column designated as 0P2. The column 1P2 indicates a true state of operation and the-column 0P2 indicates a false state of operation. When the F2 flipflop has to be triggered from thetrue state of operation to the false state of operation, an indication of l is placed under the column designated as'.0F2. Similarly, when the flip-flop must remain in the true'state of operation, an indication of 0 is placed inthe' column desig nated as 0P2. This indication of 0" shows that under no circumstances can a triggeri'ngsignal be introduced to the flip-flop to produce the false state of operation.

By Way of illustration, in rule 3.'the F2 flip-flop must be changed from a true state of operation at the end of the i time interval to a false stateof operation atthe end of the t time interval. This maybe seen by comparing the Sb and Rd. columns. I 'At" such times, atriggering signal indicated by a binary value of 1 must be introduced to the 0P2 terminal. In'rule 1, the F2 fiip flop is false at the end of the 1 time interval and'it must remain false at the end of thet interval. lnorder'to obtain this state of operation of the'FZ flip-flop, no signal can be introduced to the 1P2 terminal, as represented by an indication of 0-in the first horizontal row under the column 1P2.

The logical equations controlling the operation of the F1 and F2 flip-flops may now beseen from :Table VIII and the previous discussion. As be seen from rule 5, the F2 flip-flop is triggered from the false state to the 20 true state at the t correction time interval when Q, C and F1 are all simultaneously false. The F2 flip-flop is also triggered true when Q is false and C and F1 are simultaneously true in accordance with rule 10. This causes an expression 1F2=T.Q.C.F1+T.t.C'.F1 to be obtained. During the time intervals :8 t and t T is false. Upon the occurrence of such time intervals, 1P2 is triggered in accordance with the first term of Equation 20F2 set forth above. This equation may be written as:

The logic controlling the triggering of the F2 flip-flop to the false state at the correction time interval A, may also be seen from Table VIII. As will be seen from rules 3, 4, 7 and 8, the F2 flip-flop is triggered from the true state to the false state every time that the F2 flip-flop has a true state during the t time interval. Because of this, 0F2=T.F'2. During the t t and t time intervals, the F2 flip-flop is triggered false in a manner similar to that expressed in Equation 20F2. This triggering may be expressed as OF2=E.(Q.O"+Q.C)=T.(Q.(7+Q.C).

Table VIII also provides an indication as to the manner in which the F l flip-flop is triggered to the true state at the correction time interval 1 As may be seen from rule 3, the F1 flip-flop is triggered true at the 1 time interval when Q and F2 are simultaneously true. The F1 flip-flop is also triggered true from the false state in accordance with rule 9 when C is true at the correction time interval t.,. The inclusion of the logic T.C. would be normally expected to cover rule 10. However, it will be hereafter seen from the logic for 0P2 that the F1 flip-flop will be triggered from the true state to the false state in accordance with such logic. For this reason, the triggering of the F1 flip-flop to the true state at the correction time interval t; can be expressed In accordance with the logic expressed in Equation 20F1, the triggering of the F1 flip-flop to the true state at time intervals 2 t and t can be expressed as As may be seen from Table 'VIII, the F1 flip-flop is triggered from the true state to the false state at the cor} rection time interval 1 every time that F2 is false during this time interval. This includes rules 2, 6 and 10. For this reason, the logic for triggering the F1 flip-flop to the false state at time interval L, can be expressed as The logic for triggering the F1 flip-flop to the false state in the time intervals other than t; is obtained from Equa tion ZOFl and may be expressed as 0F2=E.F =LT'.F

In a similar manner the correction functions for subtraction may be derived from Table IX as follows:

Table IX Db Rule Difier- Db Db R11 Rd G 1F2 0F2 lFl 01 1 once F2 F1 F2 F1 6 (0,1) 1 0 0 0 0 0 0 0 O 7 (2,3) 1 0 0 1 0 0 0 D l. 8 (4, 5) 1 0 1 0 0 1 0 1 1 9 (6,7) 1 0 1 1 0 1 0 1 0 10 (8,9) 0 0 0 0 l 0 0 0 $21518 Irshamed The logic set forth immediately above may be seen from Table IX. As may be seen in Table IX,- 'the'-F2 flip-flop is triggered from the false state to the tr'ue state only in accordance with rule 10. The logicf expressing such triggering may be expressed as lF2=TQ.C* The triggering of the F2 flip-flop to the true state intim intervals t t and t is similar to that expressed above-inthe.

equations after Table VIII.

The F2 flip-flop is triggered false at correction time h interval t in accordance with rules 1, 4, 8 and9"of'Tab le IX. This occurs when either Q, C or F1 is falseat the correction time interval t This can be express dm 0F2=T.(Q+(7+F1). As will be seen, this logic does from a false state-to a 'true stateat-c0rrectiontime interval 1 when the F2 rflip-flop is true. a logic; may: be

'- expressed as lFl fliF It-willbe seen that thislogic already in the true'state at the -beginning of -correction *time interval t Inaccordance with' 'rules l,"5 and 7--of- Table IX; the

J F1 flip-flop "is triggered from the' true state to the false state at correction"- time interval :1 1 This occurs when bothcC' and= F2' are simultaneouslytrue --'or when both C 11 and FZ aIe simultaneously false. I This maybe-expressed as-0Fl T.(C.F -l-=U.F As-it willbes'een, the logic set fortli"in"the"previous equation alsocove'rs -ru1es-.4,-"=6

and 10. Theses'itu'ati'ons"do"'n'ot prdduceany errors since the" Fl-flip-fiop remains false-from timeinterval 1 10 time I intervallt inithesesituations.

Introducing the' si'gnals ='S- and Sethecombiaed addsubtract functions may be expressed as follows:

rrz'zugic-lidiets rm sirieicr egofdr -WHams ers sincethe 0: input function f or flip fl op E2 appears-simb lar torthe complement ofi its 1 input -function a setting function :is more" economical, although .a complementer circuit is required. The combined add-subtract setting I FZ T-TK QlOl-"QQ -F,.T,.(Q.G.F .F'

. V 7 C.F .F )+S.'T.(Q.C;F .F +Q.F' =.-"Q.C.'(T-FS.F ;F )+Q.C.(T+

I} H I SF F +F .(T..C.F +S.T.Q) Q.C:T-| Q.C.S.E .F +Q.G;T+

Q.(7.S;F ;F +F .T.S.C.F -FF .SLTEQ it is believed that thesetting expression tOFZ may' be derived-bya per'sonskilledin the art from TablesVIII and IX and from the above discussions. This is especially =true'in viewof the discussions above for the partial changin'g functions- '1F2,-0F2,' 1F1 and 0P1 for the cireuitry sho wn in Figure 3 and in view of the previous discussions defi'ning' and-"exemplifying setting functions. A mecham'zationof these functions is illustrated in Fig; 3 wherein :gatingcireuits '30C,'-30Q,- 30R, 30F1 and 30F2 are mechanized according to the following functions:

(30F2) t F2 '(Q.C.T+Q.C.S.F .F +Q.C'.T+

Q.0 .;F .F }'-F .T..C.F +F .S.TtQ).Cp The initial equation for lOcorrespondsto Equation 20C set forth above. The final expression for IC f'ofEquation 30C is obtained by substituting the logic for Cd in Equation 20C. The expression for Cd is set forth above between Equation 20Q and 20R. The'equation for t Q -in-the firstline of Equation 3OQ corresponds to Equati0n ZOQ representative of i Q. The final expression for--t Q'in Equation 3OQ is obtained by substituting the 1ogic---for Cd" and (3d in Equation ZOQ. The equations 'for Cd-"and Gd are set forth' above between Equations 1 ZOQandZOR.

Equation 30R c'o'rresponds in the first line" to EquatiOnQOR. The final 'logicof Equation 30Ris'obtained 'by recognizing that Cd= E"and Cd=E and bysubstitutihg the'l'ogic for Cd and Cd in Equation 20R.

The circuit shown in Fig. 3 is mechanized according togating functions requiring only two levels,1and thus is'suitable for u'se in a system where low power flip-flops are utilized such as flip-fiop comprising miniature tubes or transistors. It will be understood, howeverpfthat 'forcer'tain 'appli'cationsit may be desirable to mechanize a factored form of the equations in order to economize on gating elements. The manner in which the circuit of Fig. 3 is mechanized according to these functions should beapparent from the examples considered.

Prhapslhe most attractive feature of the resultafrom- -carr y adder-subtractor isthat when it is-utilized'in connbination with binary-coded decimal correction 'circui ,tlie

correction operation may be divided into two parts, on

a time-sharing basis. As a timing convention it is asinclude the last horizontal row of rule 9, the term A.B sumed that the two divisions of the correction are repreis included. The term I is not included in AB. since sented by the signals T =l and T :1. When T is a carry is obtained when both A and B are true re- 1, signals Rb and Rb are in flip-flops F1 and F2 gardless of whether the correction time interval t isbeing shown in Fig. 4 and flip-flops Q and C produce signals 5 presented or a difierent time interval is being presented. indicating Rb The signal R11 must then be determined No special logic has to be included for the first horias a function of input signals A and B and the carry zontal rows of rules 6, 7 and 8' since the C flip-flop is signal C; R11 being 1 whenever one of A, B and C is initially true and remains true for these situations. 1 or all signals A, B and C are 1. A decimal carry of occurs when the sum of the Table IX-A indicates the time sequence forpresenting 1 input quantities A and B has a decimal sum less than and combining the various signals in the embodiment 10. As may be seen by comparing the operational shown in Figure 4. 1 state of Q at the beginning of i with the operational The gating functions required to produce the decimal state f Q at th beginning f th C flip-flop remains signal (represented as below) and a wmPaYISOB false in all possible combinations of signals except for signal corresponding to the fourth decimal digit, at the the first horizontal column f rule 5 The logic time that '1 is equal to 1 are derived from Tables X trolling the triggering of the C fli fl from the true and XI shown below. It is considered that the manner of state to the false State in the first horizontal column 0f derivation should be apparent from the procedure out- 1 rule 5 may be expressed as 0C=A.B.Q.F The logic lined above.

Table X Sb =Q.C+Q.C T =1 T ,:1

Rule Sum A4 B4 C} Q; Sb =F Sb Sb Gd Qdi Sdi IO 00 1Q 0Q,

(0,1) 0 0 0 1 0 0 o 0 1 0 0 0 (2.3) 0 0 0 1 1 0 0 0 1 0 0 0 .5) 0 0 0 0 0 1 0 0 1 0 1 ,7) 0 0 o 0 1 1 0 0 1 0 1 .9) 0 0 1 0 0 0 1 0 0 1 .1 o (8, 9) 0 1 0 1 0 0 1 0 0 1 0 1 (8, 1 0 0 1 0 0 1 0 0 1 10,11) 0 0 1 0 1 0 1 1 0 0 10,11) 0 1 0 1 1 0 1 1 o 0 (10,11) 1 0 0 1 1 0 1 1 0 0 ,13) 0 0 1 1 0 1 1 1 0 0 2, 3) 0 1 0 0 0 1 1 1 0 0 12,13) 1 0 0 0 0 1 1 1 0 0 14,15 0 0 1 1 1 1 1 1 0 0 (14, 15) 0 1 0 0 1 1 1 1 0 0 14,15) 1 0 0 0 1 1 1 1 0 0 1 0 (16,17) 0 1 1 0 o 0 o 1 0 0 0 0 (16,17) 1 o 1 0 0 0 0 1 0 0 0 0 17) 1 1 0 1 0 0 0 1 0 0 (18,19) 0 1 1 0 1 o 0 1 1 1 0 (18,19; 1 0 1 0 1 0 0 1 1 1 0 1 (18,19 1 1 0 1 1 0 0 1 1 1 1 .0

controlling the triggering of the C flip-flop to the false state at times other than t may be expressed as in accordance with the logic previously set forth in Equation 100. 1 7

- Certain of the rules set forth in Table X have more than one possible combination of signals. For example,

each of rules 5 to 10 inclusive has three different possibilities of'combination. Rule Swill be considered by way of illustration; It will be seen that the combinations signals are combined at correction time interval 1 This may be seen by the indication of 1 :1. At this correction time interval, the quantities A B C Q and Rb are combined in accordance with Table IX-A. These quantities are indicated respectively in the 3rd, 4th, 5th, 6th and 7th vertical columns of Table X. The 8th and 9th vertical columns respectively designated as Sb); and Sb are included on an implied basis to indicate the possible binary combinations of the input quantities A and B so that the proper values of the decimal carry Cd and the comparison quantity Qd can be determined.

As will be seen, a decimal carry of 1 is obtained when the binary sum of the input quantities A and B has a decimal value greater than 10. The C flip-flop is triggered true at such times in accordance with the logical expression of S12 Sb and 8b., remain the same for each of the three variations of rule 5 since Sb Sb and Sb; indicate a binary sum of either 8 or 9. Because of the fact that Sb is 0 in rule 5, either Q, or C must be 1" but both Q and C cannot be simultaneously 1 or O." Furthermore, a binary value of 8 or 9" can be obtained by having either A, or B, be 1 but by not having both A; and B; be 1. This results from the fact that A has a binary value of 8 and B has a binary value of 8. A decimal value of 8 can also be obtained by having A and B; be 0 since values of 8 can be obtained by adding decimal values of 4 and 4 and other combinations of two numbers each less than 8.

The vertical column designated as Sd in Table X indicates the binary value of the digit of greatestsignificance when the binary sum of the two quantities A and B has been converted to a binary-coded decimal basis. For example, Sd; has a binary value of 1 for decimal values of 8" or 9. However, for values between 10 and 16 811; has a value of 0 since the decimal value is indicated by combinations of signals for S11 Sd and 8:1 and a decimal carry of 1 for Cd to the first binary manages? 25 digit of the next decimal number? Decimal values of 18 pr 19 are indicated by a binary value of 1" for 18d and a carry of 1" for Cd.

Theyalue of Sd "is determined bya combination of Cd and (M As may be=seen in Table X, a binary value of 1" for 8d,; .is obtained when both Cd and Q11; are 0 or when both Cd and Q21, are 1". Table X also Lindicate's that a binary value-rot '0? is obtained fo'r Sd when one of the quantities Cd .and Qd is l and the other quantity is 0. In this way, the binary value of Qd; for each rule -inable X'can be determined from the binary values of Cd -and'Sd -fl The proper value of Qd can be determined at correction time interval t by the propercombinations of signals A Bg,--C,.andF. For-example; Qd becomes 1 or remains 1 in rules 1 to 4, inclusive, when A B and C are simultaneously false. The Q flip-flop also becomes trueonremainsa-truein accordance with :all of the examples of .rule' when: F 118 "true at the time that-at leasttwo of -the quantities A B and C are true: This can be writtenlas The. Q. 'flip-fflop becomes. triggered false :under certain circumstances .in the correction time intervalut to .indicate .a value .of 0? for-Q21; This occurs inrules .5 to 9, ,inclusive of Table X. As will be seen, either A or B or C. is true ineachiofthese rules. Furthermore,

.at least one ofsthewquantitiesfiA, B. and .F2 is false in each of these rules. Because of this,-the Q, flip-flop becomes triggered false .in accordance with the logical exalternatives as ses tmnwibovein ratste X and disclosed in connection with that table. w I

One of the columns shownin Table XII represents the decimal carry Cd; Forzn'eg'ative numbers, the value of Cd is "l" tozindica'te a negativle carry from the most significant POSitiOl'lrOfI the firstrdecimal kiigit to the least significant: position of the-next decimal digit. Forpositive values -between 0 and- 9'," the: value of the decimal carry Cd is 0"to COHfOlIflFWiIh thetcorrespondingdecimal values inTableX. s

In accordance with rules 1 to '5, inclusive, the C flipflop is triggered-."from theaialsestaste-,to the true state at correction time t only when A is false at the same time that B isatrue; Since--thiss-samelogic prevails at time intervals other than 1 the term T does not have to be included in.ithe l6gi1.foi-11Q." Similarly, the C flip-flop is triggered from the true state to the false state when A is true at 'rthe-timenthat Beiis zfalse. Since this same logic prevails at time intervals other thant the term t does not*l1'aveto -b' anaemia-the logic-for 0C.

At the same time the; new igi rals C and-Q areformulated-,' as indicated above,'-" signals {R 5 an'd R-b are shifted forward iritdfiiiifldpsFfil and F1 respectively. Thus,'when?'I 18811112112101 'signals corresponding to the Q.G+ 017-; since' the I t idir-iatmadeiinrsignals Q, 3

Table XI is similar to Table X in the presentation-of the various quantities. However, Table XI covers the i subtraction of B from A whereas Table X covers the addition of B to A. Almost all of the quantities in Table 7 0 XI have designations similar to those set forth in Table X. However, certain columns are designated as D12 and Db to indicate the binary difference between A and B in the two most significant digits. A plurality of-examples are also given for certain rules to cover various" Candi at the-time Tlis,, l ,.soe that.no.further correction is required.- The gatingl-function -ffor .fiip' flop F1 and that defining signalRd? are derived fronrlables XII and XHI below, indicating Taddition,-and-subtraction :-corrections, respectively. 1

, Table XI I Rule Sum Cd on ism $56 s5 so Rd" 1F1 OFI 1 1M; Fl-1 r1" 1 (0,1 0' 1 0' 0 '0 0 '0 2 2,3 0 1 0; o. 1 o s (4,5 o -1 o" .1 o 1 1 4 (6,7) 0 1 0" 1 1 1; 5 (8,9) 0 fo '1; 0 0 V o 6 (10,11 1 -'0 0; o 1 0 1 5 7 12,13 1 go o 1 o o? 8 14,15) 1 0 '0 1 1 11 9 16,17 1 ot- 0 o 1: 1 10 18,19 1 1 1r o 1- 0 127 '28 .Table XIl'Continued Table XllL-Coritinued o Q1 1 1 111 1 I i Q 1 011 o Q F2 11 1 o c 1 2 on e 5 0 1 o o o 1 0 1 1 0 0 o 1 0 1 v 1 0 1 1 1 0 1 1 o 1 o 1 1 1 0 o o 0 o o 0 1 0 0 1 0 1 o o 1 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 o 1 o 1 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 o x v Rd=T.F +1 .(C.FF+0.F =1.F +0.F +T.C.F =T -F +T.C.F +(7.F

. 1F1=F 'lFl TL!" 1'. 0.1" Cd? i 11F1=r fi+r4cn+am E' =T*.F=+T .C.1=' +O.F= op glgpz+ qpa pa Table XIII includes quantities similar to those shown O i in Table XII. However, Table XIII relates to the sub- Table XI lndlcatcs 1 fi lndependelgt Vertical quantracfion of the quantity B from the quantity A whereas tit es C Q 4: n fi Wmbmed at Table XII relates to the addition of the quantity B 11011 u mml'vfll g tqproducejhe l p quafltltlfs to the quantity A, Certain of the quantities in Table 4 's; T1115 1 a p between the XIII are obtained from Table XI. These include the ferent q u y be seen 19m T l IX+ set forth quantities Cd, Qd Db ,F2 and F1. At correction time Q Independent q n i Cd, Q e f s and i z t the quantity Db in flip-flop F1 is converted to the are copied from Table X. Th a lsfimred m quantity Dd; representing the second binary digit of the the F2 flip-flopat the a d 0f l-} 1 Interval a difierence quantity on a binary-coded decimal basis. and Rb, value 1s stored in the'Fl' hip-flop at the The quantity Dd =Rd is obtained at correction time ilme- The 4 l: Qbtamed 111 the q interval I; when C is true at the time that F1 is false or meat shown in s c 4 buns gc ged 0: 1 a: p g when 0 is false at the time that F1 is true. Thus basis to indicate the pattern of S 3 an S 4 or t e decimal sums shown. in the .second, vertical column of Table XII. I The F1 flip-flop is triggered during correction time During correction time interval t the signals 1n the interval t into a pattern of operation representing the F1 flip-flop are converted into a proper form to reprethird digit of the diflerence quantity on a binary-coded sent the second digit on a binary-coded decimal basis. decimal basis. Since this digit has a weighted significance This digit has a binary significance ec ual to a decimal of 4 or 0," the F1 flip-flop should be triggered true value of 2 or "0." Because of this, Rd: should be for decimal values of 4 to 7, inclusive. The F1 flip- 1 for decimal values of 2" or 3, decimal values flop should also be triggered true for negative values of of 6" or 7, decimal values of 12 or l3 and 40 3 to 6, inclusive, since these decimal values are decimal values of 16" or 17. Such binary indications equivalent to positive values of 6 to 3, inclusive, and of 1 occur for Rd, at correction time interval i; when 1 Y a decimal can-y of 1 when the decimal complements C is false at the time that F1 is true or when C is true of the numbers are obtained. It will be seen from at the time that Fl is false. This may be represented Table XIII that the F1 flip-flop is triggered true from a as Rd =T .(0.F +C.F). false state in accordance with rules 4 and 8 and that the F1 flip-flop remains true in accordance with rules 3 the Bresentauonpf collrectmn time Interval and 9. In each of rules 4 and 8, the F2 flip-flop is e value Sb, 1n the F2 flip-flop 1s converted to the value S 3 for transfer t0 the F1 flipflopk The F1 flip flop true such that 1F l F2. The F1 flip-flop 1s trlggered false is triggered in a pattern set forth in the vertical column & g a gg gs z g fi ga f gi 81165 gg designated F1 in Table XII. As will be seen, the F1 simultaneousl false in rule u an are flip-flop is triggered from a false state to a true state in a y accordance with rules and 9. Rule 3 may be repre- 0F1=T .(C.F +U.F sented f F7172 rule 9 may be represcated as 7 And the combined adder-subtracter functions defining N loglc reamed rules 4 8 flmgh gating circuits 40c, 40o, 40R, 4on1 and 4on2 shown in 1st truei1 fgxx'n those rules since F1 continues in a true state Fig 4 may be expressed as follows: 7 a suc es. v The F1 i fl i l i d f h true state (400) 1C=[S.T .(A +Bl (F +Q)+.A.B+S.A.B].Cp to the false state at certain times during correction time 0c:[1 },(S.A+.Z.Q.F Ts 1 interval t.;. This occurs in accordance with rules 2, 6 6O and 10. Each rule may be characterized on a common 1) nQ=[ i- )43-1- basis in that the F2 flip-flop is false. +F .T .(.B.C+S.B.Q+S.B.Q].Cp

' Table XIII Rule 7 -1 c'd-c' 6. n b m m Db=F1 Db =F1' Rd 11 1 0F1 Difference 1 -01, o 0 1 o 0 o o 0 o 2 7,11) 0 1 o u 1 o 1 1 a a (5,6; 0 1 0 1 o 1 o 1 4 a,4 o 1 o 1 1 1 1 0 a --(1,2 0 0- 1 0 u 0 0 0 s (0,1? 1 0 o o 1 o 0 1 7 2,3 1 0 o 1 0 o 1 3 gas) 1 o o 1 1 1 o o s 0,7; 1 0 oo 0 1 1 1o (8,9 1 1 1 o 1 0 o 1 engages? From the foregoing description, itisapparent thatthe ;...present invention provides: a,..novel resultrfromcarry binary adder-subtracter which may be utilized withv binary coded correction circuits, .obviating .the -necessity...of. a :separate true binary result generating-network/ It .has been pointed out that the.comparison.;fiipeflop..which: is utilized also functions as a:bufier stage.and,.therefore, it is not, in a practical circuit, an additional flip-flop stage. It has also beenestablishedthatin using.,result- Lfitom-carry binary adder-subtracter,-..it ..is possible to simplify the correction circuits by, performing. the, binary --coded decimal correctionson a time-sharing basis such ..that the desired decimal carry signals and .fourth binary -..digit. of the decimal .resultare formed duringa first .-.time interval and the remainder-of:.the.binary..digits of .the decimal result are formedduring a. second .time interval.

The invention itself having been described .above, it is now convenient to desc'ribein detail circuit compo- .nents which may be used in mechanizing theinvention. ,-.Although one specific form of flip-.flop, and. gate, .or gate, and complementary, circuit.are.described.in -detail herein, it is nevertheless to. .be.unders tood.that -equivalent components may, ,.if desired,...be..i1tilized-.to

mechanize the invention.

Reference is now made to Fig. 5 andto the schematic -...diagram of a flip-flop circuit.which.is..,shown.therein. The flip-flop circuit is indicated by broken .lines'. 900 v...and includes a l-input circuitiden'tifiedby lead 901, .:and a O-input identified by lead 902,. a primary output -lead 903,. and a complementary output lead 904. The

flip-flop circuit of Fig. 5 is describedindetailin U.S. Patent 2,644,887 entitled Synchronizing jGenerator, issued July 7, 1953, to A.- E. Wolfe, vJr. A detailed .4 description herein of the construction .and operation of -:.i lip-fiop 900 is therefore deemed unnecessary.

Fig. 5a illustrates a method of symbolically representing the flip-flop circuit of Fig. 5. It may-be. noted that .there is a direct correspondence between-input leads .901 and 902 of Fig. 5 and. the 1. and O-inputterininals indicated in Fig. 5a; and between. the .outputleads 903 and 904 of Fig. 5 and the output terminals labeled E and F in Fig. 5a.

.Logical Boolean algebraic equations/have been employed in this description for the .purposeofexplaining the mechanization of .and and or" circuits-for gates which correspond directly to. the logical equations. Such circuits are well known in the.art,. .typical circuits being described in detail in U.S. Patent 2,644,887 entitled "Synchronizing Generators, issued July 7, l95 3,,.to, A. E. -Wolfe, Jr. Regardless of structural .variations, the functional characteristics of these logical circuits remain substantially constant in the art, i.e., a logical andlcircuit produces an output signal only when signals .are simultaneously applied to all the inputs vand a logical -or I circuit produces an output signal when a signal is applied -to at. least one of its inputs. Logicalgating circuits have been fully described, for. example,'inv anarticle entitled Diode Coincidence and MixingCircuits. in Digital Com- ;zputers by Tung Chang Chen in Proceedingsof the Institute of Radio Engineers, May 1950, on pages.5 -.5l4.

7; Reference is made to Fig. 6 wherein-there. is shown byway of example a typical logical ;*andcircuit 910 .1 indicated by broken lines and having .twoinputs 911 and 912 coupled by diodes 915 and 916, respectively, to a common junction 913 which is connected by means of a resistor 914 to a 13+ supp1y,the common junction 913 forming a single output. I As indicated, input 911 titrated in Fig. 6a.

- 5 910 functions typically in that asignalrappears. onoutput lead 913. only when signals -are.applied simultaneously -.:to inputs 911- and'912. Where an additional input. is -required it maybe added to the circuit of Fig. 6% by--the .--addition of an additionaldiode connected to'thecommon -10 junction point 91am a manner similar to thatgofi diodes 915 and 916. lnorder to clearly illustrate the-orientation of the-input andtoutput leadsofa symbolically-. repre r sented and circuitand' the typicalfiandicircuitiof Fig: 6, a symbolical representation of an fand -circuit is,-- -,il-lus It should be noted that athevinputs and outputs associated with thecircuit'v ofFig..-.6 ;and the. symbolically represented logica ,;and. ,circuitgof Fig. .6a. are similarly orientated.

Reference is now "made to Fig. 7. wherein there isiil-lus- QOtrated a typical logical or circuit 920- indicatedt by broken lines. and having two inputs 921.and,922 1.coupled by-diodes 924 and'923, respectively, to a -commonjunction 925 which is connected by means of a resistor." 926 to ground, the common. junction 9.25 forming the. single '25 output. As indicated in the figure, input .921 is applied to the anode of diode 924-, and input .9221is;.applied; -to the anode of diode 923, the cathodes vof.both.diodes.923 and. 924 being commonly connected to the outputterminal 925. .The. logical for circuit '920 functions .typically 0 in that a signal appears on output lead 925 when asignal is applied to either input 921 or input 922,.. or..both. Wherean additionalinput is required, it. may .be... added tothe circuit of Fig. 7 by the. addition of an additional vdiode connected to the common junction point925. in a manner similar to that of diodes 923v and 924. .Agaiir it should be noted that the inputs andoutputs. associated 'with the circuits of Fig. 7'and a symbolically represented logical or circuit of Fig. 1 aresimilarly.orientated in Fig. 1. In Fig. 7a there is presented a symbolicrepresentation of the logical or. circuitillustratedin Fig 7, wherein the inputs 921 and 922 and the single.-.output 925 of Fig. 7 is provided with similarly orientated. leads in Fig. 7a.

The operation and characteristics of the .logical ffand circuit 910 of Fig. 6 and the logical for Ecircuit920-oi Fig. 7 are fullydescribed-in detail in the. ab0ve.-men- 'tioned Wolfe patent, therefore, furtherexplanatiomci the circuits of Figs. 6 and 7 are not required here.

Reference is now made to Fig. 8 wherein there. is shown a complementary signal generating. network. may be utilized as any one of the complementer, circuitsjCo of Figs. 1-4, and to Fig. 8a which shows a. symbolic..1:epresentation of the network of Fig. 8. In the circuitiof Fig. 8, the complementary signal generator network 930 is responsive to binary or. two-level voltage control. signals applied at a first input terminal 932 for selectively gating .or passing an electrical pulse or clock signal: applied .at a second input terminal 934 to produce two, complementary electrical pulse output signals at a first output terminal Y949 and a second output terminal 939, respectively.

Complementary signal generating network 930incl'udes first and second electronic gating circuits. 940,.and 9.42, respectively, responsive to different predetermined yoltage levels of the applied control signal for selectively. presentingthe applied electrical pulse. signal atftoutput .terminals 949 and 939, respectively. I First gatingicircuit 940 includes a pair of unidirectional current. devices, ,such as crystal diodes 944 and 946, the cathodeof diodflii t 0 .being connected to input terminal 934. and. the. cathode of diode 946 being connected. to control..;terminal ;932. Diodes 944 and 946 havetheir anodesconnected together at a commonjunction 948 which is connected to utput terminal 949. Common junction 948 tiSg alsogeoupled .to one terminal B+ of a source of;biasing;pot ential,einot 31 shown, by a biasing resistor 950, the other terminal of the source being grounded.

Second gating circuit 942 also includes a pair of serially connected unidirectional current devices, such as crystal diodes 952 and 954, interconnecting common junction 948 with output terminal 939, the cathode of diode 952 being connected to common junction .948 and the anode of diode 954 being connected to output terminal 939. The common junction 956 of diodes 952 and 954 is in turn coupled to injut terminal 934 by a capacitor 958 and to one terminal B+ of the source of biasing potential, not shown, by a biasing resistor 960.

In a similar manner, diode 954 has its anode coupled to one terminal E of a source of biasing potential, not shown, by a biasing resistor 962. The other terminal of each of the sources is connected to ground. The function of the biasing potentials at terminals B+ and E, and typical values thereof will be described in detail below. For reasons which will become more clearly understood later, however, it should be stated that the potential appearing at terminal E is lower than the potential at terminal B+.

In operation, input terminal 934 is connected to a source 964 of negative electrical clock pulses Cp to be selectively passed, and control terminal 932 is connected to a variable potential control or binary signal source, such as a squarewave signal source 966 which controls the selectivity of gating circuits 940 and 942. Source 966 may be any suitable source of a signal having alternate relatively high and relatively low voltage levels, such as a conventional voltage state gating matrix.

- Referring now to Fig. 8b, there is shown a composite diagram of the waveforms appearing at various points in the complementary signal generating network of Fig. 8.

The control signal, generally designated 966, which is appliedto control terminal 932 from source 966, includes alternate relatively low and high voltage levels E and E respectively, the voltage level E corresponding substantially to the biasing potential at terminal E The negative electrical pulse or clock signal Cp, generally designated 964', which is applied to input terminal 934 from source 964, has a steady state voltage level which is preterably substantially equal to potential E the periodically recurring negative pulse excursions of signal 964 lowering the potential of the signal accordingly.

Assume now that signal 966 is initially at its low potential value of E as shown at time t in Fig. 8b. Under these conditions the signal, generally designated 949', appearing at common junction 948 will be at a voltage level substantially equal to level E due to the clamping action of diode 946. In a similar manner, the signal, generally designated as 956 appearing at common junction 956, will have a potential value substantially 1 equal to E due to the clamping action of diode 952.

Consequently, the potential difference across diode 954 in second gating circuit 942 is substantially zero volts, whereas diode 944 in first gating circuit 940 is back-biased by substantially the voltage differential between the voltage levels E and E Consider now the behavior of complementary signal generating network 930 when signal 964' includes a first negative pulse 964a, the pulse amplitude being equal to or less than the voltage differential between voltage levels E and E Since the amplitude of pulse 964a is 'insulficient to drive the cathode of diode 944 below voltage level E it is apparent that diode 944 will remain back-biased. Accordingly, diode 944 will not pass the tor 958. It is clear, of course, that diode 952 will be immediately back-biasedfor the duration of pulse 96.44;,

32 since its cathode-is held substantially at level E due to the clamping action of diode 946, whereas its anode will fall below potential E by approximately the amplitude of pulse 964a. It follows then, that pulse 964a is inhibited from appearing at output terminal 949 by backbiased diodes 944and 952.

It is clear, however, that diode 954 is new frontbiased by the application of pulse 964a since the potential of common junction 956 and hence the cathode of diode 954 is driven below the voltage level E by the magnitude of the applied pulse. Accordingly, negative pulse 964a will be passed by diode 954 and will result in a corresponding negative pulse 939a in the signal, generally designated 939', which appears at output terminal 939.

Assume now that signal 966' swings to its relatively high level potential value E and that signal 964' is at its steady state level E Under these conditions, the potentials at common junctions 948 and 956 also swing to voltage level E due to the clamping action of diodes 946 and 952, respectively. Consequently, the potential difierence across diode 944 is first gating circuit 940 is substantially zero, whereas diode 954 in second gating circuit 942 is back-biased by substantially the voltage differential between the voltage levels E and E Let us now assume that signal 964' includes a negative pulse 96415, the amplitude of which is equal to orless than the voltage differential between voltage levels E and E It is immediately clear that diode 944 will be front-biased and will, therefore, pass pulse 96412 and produce a corresponding output pulse 94% in signal 949' appearing at output terminal 949.

Although pulse 964b' is also applied to common junction 956 by coupling capacitor 958, it will be noted that the pulse 956b appearing in signal 956' does not lower the potential of common junction 956 below potential level E Accordingly, diode 954 will remain backbiased and thereby inhibit the applied negative electrical pulse from appearing at output terminal 939.

If signal 966 applied to control terminal 932 of complementary signal generating network 930 again swings to its low potential value of E as illustrated in Fig. 8b, a negative pulse 9641? applied to input terminal 934 will again produce a corresponding negative pulse 939c' at output terminal 939 and will be inhibited from appearing in signal 949' at output terminal 949. It is clear, therefore, that complementary signal generating network 930 is responsive to the relatively high and relatively low potential levels of control signal 966 for selectively passing negative electrical pulses applied at input terminal 932 to produce two complementary output signals at output terminals 949 and 939, respectively. In other words, an applied electrical pulse signal will be presented at either output terminal 949 or at output terminal 939 depending upon whether control signal 966' is at its relatively high potential value or its relatively low potential value, respectively.

As set forth above, diode 946 and resistor 950 are utilized for clamping common junction 948 at substantially the instantaneous voltage of control signal 966'. However, diode 946 also performs the additional function of inhibiting electrical pulses appearing at junction 948, such as pulse 94% in signal 949, from being applied back into squarewave signal source 966. For example, when electrical pulse 96412 is applied at input terminal 934, the potential of common junction 948 drops below its clamped potential level E by the voltage amplitude of pulse 94%. Since the potential E is being applied to the cathode of diode 946 at this time, diode 946 is backbiased for the duration of pulse 9491), thereby effectively isolating source 966 from clock pulse source 964. The combination of diode 946 and resistor 950 may, therefore, be termed an isolating network.

It will be recognized by those skilled in the computer art that if square wave signal source 966 comprises a 

